The present invention relates to electrically erasable, programmable read only memory (EEPROM) and nitride, programmable read only memory (NROM) cells in general, and particularly to reducing effects of secondary injection in NROM cells.
Floating gate memory cells are used for electrically erasable programmable read only memory (EEPROM) and Flash EEPROM cells. Reference is now made to FIG. 1, which illustrates a typical prior art floating gate memory cell. The floating gate memory cell comprises source and drain portions S and D embedded in a substrate 5 between which is a channel 7. A floating gate 8 is located above but insulated from channel 7, and a gate 9 is located above but insulated from floating gate 8.
For most floating gate cells, the standard electron injection mechanism for programming is channel hot electron injection, in which the source to drain potential drop creates a lateral field that accelerates channel electron e1 from source S to drain D, as indicated by arrow 6. Near drain D, the high energy electrons e1 may be injected (arrow 4) into floating gate 8, provided that the gate voltage creates a sufficiently great vertical field.
There is another injection mechanism, known as secondary electron injection. As indicated by arrow 3, some of the channel electrons e1 create hole and electron pairs through impact ionization of valence electrons in channel 7 or drain D. The probability of the ionization is denoted M1 and it indicates the ratio between the channel current and the hole substrate current.
Due to the positive potential of drain D, generated electrons e2 may be collected (arrow 11) by drain D. However, as indicated by arrow 13, holes h2 may accelerate towards the low substrate potential of substrate 5. On the way, another impact ionization may occur, creating another electron-hole pair e3-h3 with probability M2. Holes h3 are pulled (arrow 15) further into substrate 5 and are no concern. However, electrons e3, called secondary electrons, may be accelerated (arrow 17) towards positive gate 9 where, if they have gained sufficient energy, are injected into floating gate 8, this event having a probability of T.
The current for secondary injection is defined as:
IS=Ids*M1*M2T
wherein Id3 is the channel current from source to drain.
Because this current is significant, some floating gate devices have been designed to enhance it, thereby reducing programming time and voltages.
The following articles discuss some possible methods to enhance secondary injection:
J. D. Bude et al., xe2x80x9cSecondary Electron Flashxe2x80x94a High Performance, Low Power Flash Technology for 0.35 xcexcm and Belowxe2x80x9d, IEDM 97, pp. 279-282;
J. D. Bude et al., xe2x80x9cEEPROM/Flash Sub 3.0 V Drain-Source Bias Hot Carrier Wiringxe2x80x9d, IEDM 95, pp. 989-992; and
J. D. Bude and M. R. Pinto, xe2x80x9cModeling Nonequilibrium Hot Carrier Device Effectsxe2x80x9d, Conference of Insulator Specialists of Europe, Sweden, June 1997.
These references discuss enhancing the secondary generation and injection generally by means of pocket implants of boron, which is an electron acceptor dopant, in the substrate 5. The pocket implants tend to enhance creation of the electron-hole pairs e3-h3, and thus increase the probability M2.
However, secondary injection is not good for all types of memory cells. For nitride read only memory (NROM) cells, enhancing secondary injection may not enhance the operation of the cell and may be detrimental.
The present invention seeks to provide methods and apparatus for reducing effects of secondary injection in non-volatile memory (NVM) devices that have a non-conducting charge trapping layer, such as NROM devices. The reduction of the secondary injection improves endurance and reliability. The present invention also provides methods and apparatus for preventing punch-through voltages from detrimentally affecting erase operations in the NVM device that has a non-conducting charge trapping layer.
In the present invention, the probability T of secondary injection may be reduced by reducing the surface concentration of an electron acceptor dopant, such as, but not limited to, boron. Punch-through voltages in erase operations may be controlled by one or several methods. For example, using relatively high negative gate voltages (e.g., in the range of xe2x88x925 to xe2x88x927 V) and relatively low bit line (e.g., drain) voltages to erase the memory cell may reduce and suppress surface punch-through. Furthermore, undesirable punch-through currents may be reduced in the substrate by electron acceptor doping far from the gate-substrate interface (i.e., the substrate surface). The electron acceptor doping far from the gate-substrate interface reduces the probability T of secondary injection. The negative gate voltage in erase helps suppress the surface punch-through problem in erase, due to the reduced surface concentration of the electron acceptor dopant.
The surface concentration of the electron acceptor dopant may be reduced and the concentration increased far from the surface by one or several methods. For example, the substrate may be constructed with a double or triple-well process. Doping of the electron acceptor dopant may be constrained to be deep in the NROM cell well or at a medium depth. This may be accomplished, for example, by a deep pocket implant of the dopant. The surface concentration of the electron acceptor dopant may be reduced by doping the surface with an electron donor dopant, such as, but not limited to, phosphor or arsenic. Although the presence of the electron acceptor dopant deep in the subsume may not reduce the probability M2 of creating electron-hole pairs e3-h3, nevertheless the distance of the dopant from the surface and far from the n+ junction may reduce the probability T of secondary injection, and reduce punch-through.
There is thus provided in accordance with a preferred embodiment of the present invention a method for forming a non-volatile memory (NVM) device, the method including forming two diffusion areas in a substrate, said diffusion areas forming a channel therebetween, the channel being adapted to permit movement of primary electrons to at least one of the diffusion areas, forming a non-conducting charge trapping layer at least over the channel, and managing at least one of movement of secondary electrons from the substrate towards the charge trapping layer and a punch-through voltage in the substrate by controlling a position of a concentration of an electron acceptor dopant in the substrate.
In accordance with a preferred embodiment of the present invention the managing includes concentrating less of the electron acceptor dopant generally near an upper surface of the substrate, the upper surface including an interface between the substrate and the charge trapping layer, and more of the electron acceptor dopant further from the upper surface of the substrate.
Further in accordance with a preferred embodiment of the present invention the managing includes concentrating most of the electron acceptor dopant generally between a position halfway from the upper surface and a lower surface of the substrate.
Still further in accordance with a preferred embodiment of the present invention the method includes constructing the substrate with at least one of a double-well and triple-well process.
In accordance with a preferred embodiment of the present invention less of the electron acceptor dopant may be concentrated generally near the upper surface of the substrate by concentrating more of an electron donor dopant near the upper surface of the substrate. The electron acceptor dopant may comprise boron. The electron donor dopant may comprise at least one of phosphor and arsenic.
Further in accordance with a preferred embodiment of the present invention the non-conducting charge trapping layer may include an oxide-nitride-oxide (ONO) layer. There is also provided in accordance with a preferred embodiment of the present invention a non-volatile memory (NVM) device including a channel formed in a substrate, two diffusion areas, one on either side of the channel in the substrate, each diffusion area having a junction with the channel, the channel being adapted to permit movement of primary electrons to at least one of the diffusion areas, a non-conducting charge trapping layer formed at least over the channel, and an electron acceptor dopant concentrated less near an upper surface of the substrate, the upper surface including an interface between the substrate and the charge trapping layer, and concentrated more further from the upper surface of the substrate.
In accordance with a preferred embodiment of the present invention the electron acceptor dopant is concentrated at at least 1xc3x97117 cmxe2x88x922 at a depth of 0.1 xcexcm from the upper surface of the substrate.
In accordance with another preferred embodiment of the present invention the electron acceptor dopant is concentrated at at least 1xc3x971017 cmxe2x88x922 at a depth of between 0.1-0.8 xcexcm and deeper from the upper surface of the substrate.
In accordance with yet another preferred embodiment of the preset invention the electron acceptor dopant is concentrated less than 1xc3x971017 cmxe2x88x922 at a depth of less than 0.1 xcexcm.